KREST MAJOR PROJECTS-B.Tech-ECE-VLSI

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B.Tech-ECE-VLSI

Download Project List Sno Projects List Remarks Abstract 1. An On-Chip AHB Bus Tracer With Real Time Compression & Dynamic Multi Resolution Supports For Soc (VHDL) IEEE Download 2. Reducing The Computation Time In (Short Bit-Width) Two's Complement Multipliers (VERILOG) IEEE Download 3. Self-Immunity Technique To Improve Register File Integrity Against Soft Errors(VERILOG) IEEE Download 4. Radix-8 Booth Encoded Modulo 2n-1 Multipliers With Adaptive Delay For High Dynamic Range Residue Number System (VERILOG) IEEE Download 5. Design And Characterization Of Parallel Prefix Adders Using FPGAS (VERILOG) IEEE Download 6. Matrix multiplication & det(VHDL) IEEE Download 7. Design of AES(encryption and decryption ) using with 128 key bit (VHDL) IEEE Download 8. Design of scrambler and descrambler (VHDL) IEEE Download 9. Design of CORDIC algorithm (VHDL) IEEE Download 10. Design of DES algorithm using 64 bit length (VERILOG) IEEE Download 11. Design of CAN protocol (VERILOG) IEEE Download 12. Triple des design in (VERILOG) IEEE Download 13. Implimentation of Pulse Width Moduletion Using Sine Wave (VERILOG) IEEE Download 14. Design of Fault phase path method (VERILOG) IEEE Download 15. Design of I2C protocol (VERILOG) IEEE Download 16. SHA-1 ALGORITHM (VERILOG) IEEE Download 17. BARREL SHIFTER ( VERILOG) IEEE Download 18. An Efficient Implementation of Floating Point arithmetic block (VHDL) IEEE Download 19. An Efficient Architecture for 3-D Discrete Wavelet Transform. (VERILOG) IEEE Download 20. A Spurious-Power Suppression Technique for Multimedia/DSP Applications(VERILOG) IEEE Download 21. Design of On-Chip Bus with OCP Interface. (VHDL) IEEE Download 22. DDR3 based lookup circuit for high-performance network processing. (VERILOG) IEEE Download 23. Multiplication Acceleration Through Twin Precision (VHDL) IEEE Download 24. Implementation of FFT/IFFT Blocks for OFDM (VHDL) IEEE Download 25. A Very fast and low power Carry select adder Circuit (VERILOG) IEEE Download 26. QPSK(VERILOG) IEEE Download 27. RCEAT for Radio Frequency Identification (RFID) UHF Tag (VERILOG) IEEE Download 28. DA-based DCT core with an error-compensated adder-tree (ECAT) IEEE Download 29. Efficient FPGA implementation of convolution (VHDL) IEEE Download 30. Design of Parallel Multiplier Based on Radix-2 Modified Booth Algorithm(VERILOG) IEEE Download 31. High Performance Complex Number Multiplier Using Booth-Wallace Algorithm (VHDL) IEEE Download 32. Design of JPEG Image Compression Standard (VERILOG) IEEE Download 33. Design of an Bus Bridge between OCP and AHB Protocol (VHDL) IEEE Download 34. Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block(VHDL) IEEE Download 35. VMFU Design Using Spurious Power Suppression Technique (VERILOG) IEEE Download 36. Implementation of High speed DDRSDRAM Controller (VHDL) IEEE Download 37. Implementation of DWT using(5,3) Lifting Scheme (VERILOG) IEEE Download 38. Design and Implementation of Systolic array Architecture for DWT (VERILOG) IEEE